Power architecture

January 30, 2014
Colin Walls

Power management in embedded systems – new thinking required

Effective low-power design for embedded-systems will take a new culture of close collaboration between hardware and software engineers.
January 28, 2014
Mark Bollar is a product marketing director at Synopsys overseeing physical implementation.

Are advanced designs only possible at emerging process nodes?

Advanced design isn’t restricted to emerging process nodes any more. Designers are using the latest tools to produce advanced designs on established nodes.
December 16, 2013
forte-hsl-2-featim

How high-level synthesis helps optimize low power designs – Part Two

Continuing our series on high-level synthesis (HLS) for low power design. Part Two details how HLS helps you make and evaluate architectural decisions.
September 3, 2013
SNPS TDF UPF hierarchy feat img

Choosing a block representation in a UPF-based hierarchical multi-voltage IC design

This article looks at the way in which various representations of a block of a design have different implications in a UPF based power-aware hierarchical design flow.
Article  |  Topics: EDA - IC Implementation  |  Tags: , , ,   |  Organizations:
September 10, 2010

Hypervisors and the Power Architecture

The use of multicore processors is on the rise to meet inexorable demand for increasingly sophisticated functionality in embedded systems. Hardware virtualization technology provides a complementary and game-changing approach to maximizing the utility of that extra silicon horsepower. The Power Architecture has included hardware virtualization support since 2001 in its server-based instruction set architecture (ISA). [...]

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