placement

October 21, 2021
Sherif Hany Mousa is a Principal Technologist in the Calibre Design Solutions division of Siemens EDA, a part of Siemens Digital Industries Software. Sherif previously held positions as a technical marketing engineer, analog quality assurance engineer, and IC design consultant for physical verification and analog/mixed signal applications. He has authored multiple publications and holds multiple patents in the fields of analog layout porting, hotspot detection and correction, and machine learning-assisted verification flows. Sherif is a senior IEEE member who holds an M.Sc. in Electrical and Communication Engineering, and is currently engaged in Ph.D. research, focusing on circuit analysis.

Advanced symmetry verification is a thing of beauty

Innovation is extending the technique's power across areas such as context-aware layout, accounting for multi-patterning and implementing fill.
Expert Insight  |  Topics: EDA - IC Implementation, Verification  |  Tags: , , , , ,   |  Organizations:
May 28, 2015

Dynamic power optimization

FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
October 18, 2014
Soft-blocked floorplan

Placement optimizations push power and clock on Cortex-M7 project

Soft blocking to prevent cell spreading and other placement-optimization techniques helped improve power and clock speed on a Cortex-M7 test chip designed by ARM and Cadence.

PLATINUM SPONSORS

Synopsys Cadence Design Systems Siemens EDA
View All Sponsors