place and route

June 1, 2010

Signoff-driven IC design

The demands of manufacturing closure at advanced process nodes make the traditional design-then-fix flow unmanageable. At 28nm and below, designers need a solution that can address manufacturing issues at any point in the design process, enabling a true correct-by-construction methodology. An effective solution must provide design-rule-check and design-for-manufacturing analysis using the actual foundry-approved signoff rules [...]
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April 14, 2010

Top-level MCMM closure for a multi-million-gate design

STMicroelectronics in Greater Noida, India recently completed an Omega2 set-top-box decoder IC targeted at HDTV markets. This article discusses how ST used Mentor Graphics’ Olympus-SoC software to address the closure challenges presented by a very large design. It describes how the design team used the tool suite’s chip assembly, concurrent multi-corner multi-mode (MCMM) analysis and [...]
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May 1, 2009

The art of low-power physical design

The architectures that underpin today’s traditional place-and-route tools are showing their age, largely because their static timing analysis engines cannot handle more than two mode/corner scenarios. Thus limited, the software struggles to effectively implement low-power design techniques beyond such established concepts as clock gating and multiple threshold voltages. Designers run into difficulties when trying to […]

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June 1, 2008

Multi-corner multi-mode signal integrity optimization

Signal integrity (SI) is an ever-growing problem as more interconnect effects and fast clocks increase the chances of crosstalk noise and glitches as well as unexpected signal delays. There has been a significant increase in SI-related timing violations due to the increasing influence of lateral wire capacitance in designs at 65 and 45nm. A fast-increasing […]

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September 1, 2007

Using multi-corner multi-mode techniques to meet the P&R challenges at 65 nm and below

Concurrent multi-corner, multi-mode analysis and optimization is becoming increasingly necessary for sub-65nm designs. Traditional P&R tools force the designers to pick one or two mode corner scenarios due to inherent architectural limitations. As an example of the problem, a cellphone chip typically needs to be designed for 20 mode/corners scenarios. In the absence of a […]

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