place and route

January 13, 2014
Interconnect resistance has increased since the 40nm node

Interconnect resistance

A number of effects have led to a dramatic increase in interconnect resistance in the sub-32nm process nodes that demands the use of smarter routing.
January 13, 2014
Multiple patterning is causing issues with access to standard-cell pins in nanometer processes

Cell pin access

Increasingly complex design rules in 14nm and 16nm make it harder to connect local routing to the inputs and outputs (pins) of standard cells.
September 24, 2013

Accelerating process migration in advanced ASIC design at Bull

How the HPC company used Synopsys' Lynx Design System to standardise its flow and simplify migration to the next node.
Article  |  Topics: IP - Design Management, EDA - IC Implementation  |  Tags: , , ,   |  Organizations: ,
October 23, 2012

Vivado, inside the new Xilinx design suite

The FPGA vendor's new flagship is now on public release. It adds an array of features, including support for system-level to HDL synthesis.
October 11, 2012
Tong Gao

The physical design challenges of 20nm processes

Manufacturability, routing, library design and more - it all needs rethinking at 20nm, writes Tong Gao of Synopsys.
Expert Insight  |  Topics: EDA - DFM  |  Tags: , , , ,   |  Organizations:
September 12, 2012

Critical tools for 20nm design

A look at the way in which key tools, in IC implementation, modeling and extraction, and physical verification, are developing in response to the challenges of 20nm design
June 1, 2010

Signoff-driven IC design

The demands of manufacturing closure at advanced process nodes make the traditional design-then-fix flow unmanageable. At 28nm and below, designers need a solution that can address manufacturing issues at any point in the design process, enabling a true correct-by-construction methodology. An effective solution must provide design-rule-check and design-for-manufacturing analysis using the actual foundry-approved signoff rules [...]
Article  |  Topics: EDA - DFM  |  Tags: , , ,
April 14, 2010

Top-level MCMM closure for a multi-million-gate design

STMicroelectronics in Greater Noida, India recently completed an Omega2 set-top-box decoder IC targeted at HDTV markets. This article discusses how ST used Mentor Graphics’ Olympus-SoC software to address the closure challenges presented by a very large design. It describes how the design team used the tool suite’s chip assembly, concurrent multi-corner multi-mode (MCMM) analysis and [...]
Article  |  Topics: EDA - DFM  |  Tags: , ,
May 1, 2009

The art of low-power physical design

The architectures that underpin today’s traditional place-and-route tools are showing their age, largely because their static timing analysis engines cannot handle more than two mode/corner scenarios. Thus limited, the software struggles to effectively implement low-power design techniques beyond such established concepts as clock gating and multiple threshold voltages. Designers run into difficulties when trying to […]

Article  |  Topics: EDA - DFM  |  Tags: , , ,
June 1, 2008

Multi-corner multi-mode signal integrity optimization

Signal integrity (SI) is an ever-growing problem as more interconnect effects and fast clocks increase the chances of crosstalk noise and glitches as well as unexpected signal delays. There has been a significant increase in SI-related timing violations due to the increasing influence of lateral wire capacitance in designs at 65 and 45nm. A fast-increasing […]

Article  |  Topics: EDA - DFM  |  Tags: , ,

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