physical verification

January 15, 2018
Physical Verification Efficiencies - featured image

Three ways to lift productivity during physical verification

How to get the best PV results by reducing computational demands; handling data more efficiently and exploiting parallelization.
Article  |  Topics: EDA - DFM, Verification  |  Tags: , , , ,   |  Organizations:
September 14, 2017
Featured image - Silicon photonics

Silicon photonics moves out of the shadows

An alphabet soup of AI, HPC, 5G and the IoT has finally seeded creation of a design infrastructure for silicon photonics.
September 10, 2014
John Ferguson is the director of marketing for Calibre DRC applications at Mentor Graphics. John has worked extensively in the area of physical design verification for the manufacture of leading edge integrated circuits.

If we’d only known then what we know now

Innovation in physical verification is driven by incoming nodes but new tools and features can and should be fed back up the technology chain.
Expert Insight  |  Topics: EDA - DFM, Verification  |  Tags: , , , ,   |  Organizations:
July 9, 2014
Intel's trigate is among the structures to be modeled by the revised BSIM4

One BSIM to rule them all

A change in the way the core compact models are developed has accelerated their development and, for the first time, allowed the models to be used not just for circuit simulation but to help guide process evolution as chipmakers play not only with materials but the shape of finFETs.
Article  |  Topics: EDA - DFM, IC Implementation  |  Tags: , , , , , ,   |  Organizations: ,
May 2, 2013
Intel finfFET SEM

Physical verification of finFET and FD-SOI devices

A look at some of the design and physical verification challenges of working with finFET and FD-SOI devices, including their impact on layout, DRC and LVS.
Article  |  Topics: EDA - Verification  |  Tags: , , ,
October 9, 2012
tdf-oct12-snps20pv-feat

Physical verification of 20nm designs through integrated double-patterning analysis and repair

Finding and fixing double patterning problems in 20nm designs
Article  |  Topics: EDA - DFM, IC Implementation  |  Tags: , ,   |  Organizations:
September 12, 2012
tdf-sept-SNPS-crit-tools-feat

Critical tools for 20nm design

A look at the way in which key tools, in IC implementation, modeling and extraction, and physical verification, are developing in response to the challenges of 20nm design

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