parasitic extraction

December 2, 2016

Hierarchical signoff of SoC designs at advanced process nodes

Hierarchical signoff strategies for large SoCs at advanced nodes can be effective if sufficient attention is paid to reflecting the impact of cross-hierarchy parasitics.
August 7, 2014
Hitendra Divecha is senior product marketing manager at Cadence Design Systems

Dealing with parasitic-extraction challenges in finFETs and advanced nodes

FinFET and 3DIC technologies bring with them not just higher performance but an increased need for accurate parasitic analysis.
Expert Insight  |  Topics: EDA - IC Implementation, Verification  |  Tags: , , ,   |  Organizations:
July 15, 2014

Parasitic extraction

Parasitic extraction reveals the impact of implementation on the theoretical performance of IC designs.
June 18, 2014
Parasitic Extraction Featured Image

Full 3D-IC parasitic extraction

How to enhance an 'ideal' parastitic extraction strategy to create a full 3D assembly-level parasitic netlist for simulation and circuit analysis.
Article  |  Topics: EDA - DFM  |  Tags: , ,   |  Organizations:
December 9, 2013
Carey Robertson is a director of product marketing at Mentor Graphics overseeing the marketing activities for layout versus schematic (LVS) and extraction products.

FinFET parasitics come under control

Extracting finFET parasitics means a shift to 3D models, field solvers for greater accuracy, and MCMM techniques.
Expert Insight  |  Topics: EDA - DFM, IC Implementation  |  Tags: , , , ,   |  Organizations:
May 29, 2013
FinFET capacitances diagram

How to design with finFETs

How to design with finFETs, including the impact on standard cells, IP, SRAM; the effects of fin quantization; extraction and parasitics; AMS issues and more.
September 12, 2012

Critical tools for 20nm design

A look at the way in which key tools, in IC implementation, modeling and extraction, and physical verification, are developing in response to the challenges of 20nm design
June 1, 2012
Michael Buehler-Garcia

DAC 2012: 20(nm) questions

There's still debate over certain aspects of the 20nm node, but the main challenges are already being addressed. Expect to see foundries and vendors mark their turf at DAC.
Expert Insight  |  Topics: EDA - DFM  |  Tags: , , , , ,   |  Organizations:
April 14, 2010

Solving the next parasitic extraction challenge

A greater proportion of the layout requires more precise extraction at the 32nm and 28nm process nodes, so rules-based extraction tools can no longer deliver the accuracy needed to confirm acceptable electrical performance. Given the nature of parasitic elements in analog and mixed-signal (AMS) system-on-chip designs, designers need a parasitic extraction tool that provides gate-level, [...]

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