parallelism

August 28, 2016
Chips on a wafer

Addressing the verification challenges of complex SoCs

Three senior verification specialists talk about how they are navigating the challenge of verifying multibillion-transistor SoCs with limited compute resource, increasing coverage demands and shrinking timescales.
June 17, 2015
Joe Mallett is senior manager, product marketing for FPGA-based synthesis software tools at Synopsys.

Eight tips for choosing your next FPGA tool

Eight issues to consider when choosing an FPGA tool, including risk minimisation, routing issues, ability to iterate, IP freedom and more
Expert Insight  |  Topics: EDA Topics  |  Tags: , ,   |  Organizations:

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