OS-VVM

May 23, 2012

VHDL

VHDL is a hardware description language with rich constructs that can model complex systems. It can also be constrained for use as the starting point of an FPGA or ASIC design.
Guide  |  Topics: EDA - IC Implementation  |  Tags: , , , , ,
May 21, 2012

Where there’s a will… there’s a way to better VHDL verification

An overview of the Open Source VHDL Verification Methodology and two of the libraries it uses.

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