OCV

May 30, 2015

Clock tree synthesis

Clock-tree generation is coming under increased scrutiny because of its role in dynamic power consumption and problems caused by on-chip PVT variation.
May 19, 2014

On-chip clock strategies and GALS

The increased use of IP and a rise in process variability is driving a move to look at alternatives to traditional low-skew clock distribution strategies.
September 6, 2013

On-chip variation (OCV)

Accounting for on-chip variation (OCV) has become a critical factor in assuring timing closure for nanometer-scale ICs and avoiding over-pessimistic margins.
Guide  |  Topics: EDA - Verification  |  Tags: , , , , , ,
March 1, 2007

Confronting chip assembly challenges

Until recently, hierarchical design flows have been favored for the implementation of multi-million gate SOCs. However the rapid increases in design size brought on by nanometer process geometries have seen engineers seek to cope with the inherently block-based nature of such flows by seeking greater concurrency between the block implementation and chip assembly stages in […]

Article  |  Topics: EDA - DFM  |  Tags: , ,

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