netlist

April 3, 2024
Parasitic Extraction

Master parasitic extraction for leading-edge designs

A comprehensive guide to parasitics, how to perform parasitic extraction and the latest technologies available for this critical task.
October 6, 2022
3D-IC Stack LVS Connectivity

Building confidence and flexibility in 3D-IC system level design

3D-IC presents major connectivity challenges in maintaining a golden netlist and managing necessary exceptions. Learn how to manage them.
Article  |  Topics: EDA - DFM, Verification  |  Tags: , , , , ,   |  Organizations:
February 10, 2016
Geoffrey Ying, director of product marketing, AMS group, Synopsys

Speeding AMS verification by easing simulation debug and analysis

How to ease AMS verification using tools that improve simulation debug, ease IP integration, and speed design analysis and centering
March 20, 2012

Blindsided by a glitch

Logic glitches in asynchronous clock domain crossing paths can arise even when synthesis tools declare a design’s RTL and gate-level netlists equivalent. This article describes Real Intent’s approach to capturing them.

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