model order reduction

June 2, 2011

Efficient RC power grid verification using node elimination

To ensure the robustness of an integrated circuit, its power distribution network (PDN) must be validated beforehand against any voltage drop on VDD nets. However, due to the increasing size of PDNs, it is becoming difficult to verify them in a reasonable amount of time. Lately, much work has been done to develop Model Order [...]
Article  |  Topics: EDA - Verification  |  Tags: , ,

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