mixed-signal

December 22, 2017
feat-im-in-design-DRC

Improve custom/AMS design and productivity with in-design DRC

In-design DRC is a technique that frees up engineers from many of the challenges of delivering AMS design under ever more complex design rules.
Article  |  Topics: EDA - IC Implementation, - Uncategorized  |  Tags: , , , , , ,   |  Organizations:
March 15, 2017
DVCon China takes place at the Parkyard Hotel, Shanghai on April 19th.

DVCon China launches this April in Shanghai

DVCon China general chair Andy Liu discusses Accellera’s new addition to its design and verification conference series (简体中文).
Expert Insight  |  Topics: EDA - ESL, IC Implementation, Verification  |  Tags: , , , , , , ,   |  Organizations: , , ,
March 15, 2017
DVCon China takes place at the Parkyard Hotel, Shanghai on April 19th.

DVCon中国将于4月在上海亮相

DVCon中国大会主席刘红亮讨论了Accellera新增的DVCon中国ASIC设计和验证会议的看点。
Article  |  Topics: Uncategorized  |  Tags: , , , , , , ,   |  Organizations: , , ,
January 30, 2015
VCS AMS feat img

Mixed-signal verification of advanced SoCs using VCS AMS

How ST Microelectronics uses Synopsys' VCS AMS, combining VCS functional verification and CustomSim, to verify one of its mixed-signal designs
Article  |  Topics: IP Topics, EDA - Verification  |  Tags: , , , , ,   |  Organizations: ,
April 22, 2014
Tech Design Forum Synopsys - semtech - featimg

Accelerating multi-corner multi-mode sign-off using the Lynx Design System

Mixed-signal chip designer Semtech on using Lynx Design System to manage multi-corner multi-mode sign-off when you've got 306 scenarios to check.
Article  |  Topics: IP - Design Management, EDA - Verification  |  Tags: , , , ,   |  Organizations:
December 3, 2012

Overcoming dummy fill deck limitations for analog design

CSR used a customized approach to automated dummy fill layout for AMS to address layer density and device matching issues in standard flows aimed at digital SoCs.
Article  |  Topics: EDA - DFM, IC Implementation  |  Tags: , ,   |  Organizations: ,
June 1, 2011

The challenge of analog, mixed-signal and custom physical implementation at 28nm

The 28nm process node has once more raised the design bar in terms of the DFM checks needed to realize a design. This is particularly true for analog and mixed-signal engineering, where rules that could once be maintained manually now need to be addressed in a more integrated, automated, and timely way. The article explores [...]
Article  |  Topics: EDA - IC Implementation  |  Tags: , ,
September 1, 2007

Designing for the real world

Lew Counts It is not unusual for analog circuit designers to exhibit a wistful air of ‘been there, done that’, even if you would never catch them wearing the t-shirt. That goes double for Lewis Counts, vice president of analog technology at Analog Devices and a fellow with the sector giant. “There are things they’re […]

Article  |  Topics: EDA - IC Implementation  |  Tags:   |  Organizations:

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