manufacturing closure

May 31, 2011

The Roadmap to LFD Value: Quantifying a Return on Investment in Calibre LFD

By the time a serious lithographic problem is identified at the fab, it is too late in the design process to make a simple layout change, resulting in a significant delay of the tapeout, and consequently chip delivery. To diminish the risk of sensitive layout structures, and avoid or reduce design delays, designers need the […]

Whitepaper  |  Topics: EDA - DFM  |  Tags: , , ,
June 1, 2010

Signoff-driven IC design

The demands of manufacturing closure at advanced process nodes make the traditional design-then-fix flow unmanageable. At 28nm and below, designers need a solution that can address manufacturing issues at any point in the design process, enabling a true correct-by-construction methodology. An effective solution must provide design-rule-check and design-for-manufacturing analysis using the actual foundry-approved signoff rules [...]
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April 14, 2010
etf-st3_medium

Top-level MCMM closure for a multi-million-gate design

STMicroelectronics in Greater Noida, India recently completed an Omega2 set-top-box decoder IC targeted at HDTV markets. This article discusses how ST used Mentor Graphics’ Olympus-SoC software to address the closure challenges presented by a very large design. It describes how the design team used the tool suite’s chip assembly, concurrent multi-corner multi-mode (MCMM) analysis and [...]
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December 1, 2009
3D stacking with TSVs

Making SiP happen in 3D

System-in-package (SiP) used to be thought of as a ‘poor man’s system-on-chip’ (SoC). Not any more. The complexity involved in implementing various levels of functionality on a single SoC is reaching such levels that it is becoming increasingly difficult to justify the design and manufacturing costs. Similarly, the need to deliver products within equally tight […]

Article  |  Topics: EDA - DFM  |  Tags: ,

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