low power

June 2, 2013

IEEE 1801-2013 (UPF 2.1)

IEEE 1801-2013 updates and refines the Unified Power Format for low-power VLSI design, reflecting changes in power modeling and verification.
April 9, 2013
tdf-calyptoamd-mar13-featim

How AMD implemented efficient clock gating analysis for Jaguar

The chipmaker used Calypto’s PowerPro to carry out power analysis of its latest core design at the RTL rather than at post-gate synthesis.
Article  |  Topics: EDA Topics, EDA - IC Implementation  |  Tags: , , ,   |  Organizations: , ,
March 11, 2013
Metastability at clock boundary

Clock-domain and reset verification in the low-power design era

The multiple clock domains on today's SoCs create a hotbed for clock-domain crossing bugs to thrive. Low-power design techniques increase the complexity of tracking these bugs down. Find out how these failures arise and what to do about them.
Article  |  Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:
October 30, 2012
Mixed-Signal Methodology Guide

Verifying low-power intent in mixed-signal design

An exclusive extract from Cadence Design Systems' Mixed-Signal Methodology Guide provides an excellent overview of its discrete topic and a flavor of the book as a whole.
Article  |  Topics: EDA Topics, EDA - Verification  |  Tags: , , ,   |  Organizations: ,
October 26, 2012
velocefeatured

Emulation delivers system-level power verification

Overcome the time and visibility limitations of simulation and of gate-level and RTL-based strategies to achieve full-chip analysis.
Article  |  Topics: EDA Topics, EDA - ESL, Verification  |  Tags: , , , ,   |  Organizations:
October 15, 2012
nvidia-chips

OpenCL: games technology comes to us all

OpenCL aims to open up the performance of graphics processors to other applications. It is also one more way in which compilation is being moved to runtime to make it easier to move code dynamically across heterogeneous platforms.
October 3, 2012

System virtual prototyping

The technique enables early software development and hardware/software co-design strategies before a project is more rigidly defined in RTL.
June 4, 2012

Sleep modes

For a growing number of applications, leakage is a major component of the lifetime energy consumption of an MCU, making it essential to shut the processor core down when it is not needed. Sleep modes help control that.
March 21, 2012
54041-Wolverine-MSP430-original

How TI halved the power consumption of Wolverine

Texas Instruments’ MSP430 microcontroller platform has been one of the industry’s leading ultra-low-power architectures for more than a decade. Each generation has been focused on setting new records. The latest, Wolverine, cuts power and energy consumption by more than half.
Article  |  Topics: Embedded - Platforms  |  Tags: , ,   |  Organizations:
March 7, 2012
tdf-nuj-thumb

Envelope tracking for RF power amplifiers in mobile handsets

‘Envelope tracking’ is not a new technique; it has been known about for more than 50 years. But it could greatly help the power consumption challenges once more facing mobile handset design.
Article  |  Topics: PCB - Design Integrity  |  Tags: , , , , ,   |  Organizations:

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