IEEE 1801-2013 updates and refines the Unified Power Format for low-power VLSI design, reflecting changes in power modeling and verification.
The chipmaker used Calypto’s PowerPro to carry out power analysis of its latest core design at the RTL rather than at post-gate synthesis.
The multiple clock domains on today's SoCs create a hotbed for clock-domain crossing bugs to thrive. Low-power design techniques increase the complexity of tracking these bugs down. Find out how these failures arise and what to do about them.
An exclusive extract from Cadence Design Systems' Mixed-Signal Methodology Guide provides an excellent overview of its discrete topic and a flavor of the book as a whole.
Overcome the time and visibility limitations of simulation and of gate-level and RTL-based strategies to achieve full-chip analysis.
OpenCL aims to open up the performance of graphics processors to other applications. It is also one more way in which compilation is being moved to runtime to make it easier to move code dynamically across heterogeneous platforms.
The technique enables early software development and hardware/software co-design strategies before a project is more rigidly defined in RTL.
For a growing number of applications, leakage is a major component of the lifetime energy consumption of an MCU, making it essential to shut the processor core down when it is not needed. Sleep modes help control that.
Texas Instruments’ MSP430 microcontroller platform has been one of the industry’s leading ultra-low-power architectures for more than a decade. Each generation has been focused on setting new records. The latest, Wolverine, cuts power and energy consumption by more than half.
‘Envelope tracking’ is not a new technique; it has been known about for more than 50 years. But it could greatly help the power consumption challenges once more facing mobile handset design.
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