low power

June 18, 2018
Andy Ladd is president and CEO of Baum. He has more than 30 years of experience in the electronics industry. Ladd received a Bachelor of Science degree in Computer Engineering from the University of Illinois at Champaign/Urbana, and a Master of Science degree in Engineering from the University of Michigan at Ann Arbor.

Power analysis isn’t just for battery-operated products

Andy Ladd highlights the wide range of peak-power concerns around plugged-in devices.
October 30, 2017
Debug case study for ARM/AXI based design

Case study: Verifying and optimizing software for power on SoCs

How emulation was used to debug out-of-spec power on a multicore ARM design using the AXI bus.
February 8, 2017
Veloce featured image for SSD Verification article

Emulation strategies for SSD verification

SSD controllers are becoming increasingly complex and as a result emulation is now the first choice for SSD verification. But your strategy must still meet five key criteria.
January 12, 2016
Angela Raucher is product line manager for Synopsys’ ARC EM processors.

Processor configuration for low-power IoT applications

Many IoT applications have a very strict energy budget. SoC designers targeting the IoT have to trade off providing the features that the market demands with the power budget the applications demand. What are their options?
Expert Insight  |  Topics: IP - Assembly & Integration, Selection  |  Tags: , ,   |  Organizations:
December 9, 2015
Emulation IoT Networking Challenges

Emulation overcomes the five main IoT and networking verification challenges

More protocols, multibillion-gate designs, minimized power, burgeoning software and, for networking, hundreds of switch and router ports emphasize the need for scalable, virtualized emulation.
December 1, 2014

Using formal techniques to help tackle SoC verification challenges

Formal techniques can be applied to various parts of the verification challenge, including low-power and clock domain-crossing issues
July 20, 2014
Rebecca Lipon is the senior product marketing manager for the functional verification product line at Synopsys. Prior to joining the marketing team, Rebecca was an applications engineer at Synopsys working on UVM/VMM adoption, VCS, VIP, static and formal verification deployments.

Rethinking SoC verification

The argument for an integrated approach to SoC verification
February 4, 2014
Featured image - virtual prototyping big.Little case study

Debugging with virtual prototypes – Part Four

The fourth installment discusses the extra levels of debug capability available when using virtual prototypes through the example of an ARM big.LITTLE-based embedded system.
December 16, 2013

How high-level synthesis helps optimize low power designs – Part Two

Continuing our series on high-level synthesis (HLS) for low power design. Part Two details how HLS helps you make and evaluate architectural decisions.
October 21, 2013
Featured image for high level synthesis LP Part One

How high-level synthesis helps optimize low power designs – Part One

Going inside HLS' basics shows how it can deliver power savings over 50% for some applications.
Article  |  Topics: EDA - ESL, IC Implementation  |  Tags: ,   |  Organizations:

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