Dynamic voltage and frequency scaling is effective for low-power VLSI design. Body or back bias can provide additional control over leakage and performance.
By taking the circuit supply voltage close to that of the threshold voltage or even below, it is possible to optimize low-power VLSI design. But there are pitfalls.
While some HW/SW co-design and verification techniques are in place, a power analysis methodology is only just emerging
The configurability of processor IP such as Synopsys' ARC HS family gives designers the option to optimise for power, performance or a combination of both.
Reset is no longer simply an 'X' issue but also feeds into power optimization. Catching issues early greatly speeds verification.
Effective low-power design for embedded-systems will take a new culture of close collaboration between hardware and software engineers.
Problems with process scaling make it seem as though the long era of innovative, lucrative hardware design is coming to an end. But is that really the case?
Mobile and networking platforms need high bandwidth, low power consumption, and small footprint. These needs drove standards, such as LPDDR4, Wide I/O 2 and Hybrid Memory Cube.
Virtualization makes it possible to run multiple operating system images on one processor core – with benefits for memory protection, power efficiency and cost reduction.
The article describes the context and need for embedded operating systems that are more responsive to the power management demands placed on today’s electronic devices. It reviews the design objectives for the two main types of power management, reactive and proactive, and examines how both can be implemented. For system developers designing portable electronic devices, […]