low-power design

May 28, 2015

Dynamic power optimization

FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
July 13, 2014
ST/CEA-Leti 'Frisbee' wide-voltage DSP

DVFS and body bias

Dynamic voltage and frequency scaling is effective for low-power VLSI design. Body or back bias can provide additional control over leakage and performance.
Guide  |  Topics: EDA - IC Implementation  |  Tags: , , , ,
May 29, 2014
Near-threshold computing for minimum energy - thumbnail

Near-threshold and subthreshold logic

By taking the circuit supply voltage close to that of the threshold voltage or even below, it is possible to optimize low-power VLSI design. But there are pitfalls.
January 15, 2012

Virtualization

Virtualization makes it possible to run multiple operating system images on one processor core – with benefits for memory protection, power efficiency and cost reduction.

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