ISE Design Suite

October 25, 2012

Vivado HLS/AutoESL: Agilent packet engine case study

How Xilinx' Vivado HLS enabled the creation of an in-fabric, processor-free UDP network packet engine
October 23, 2012
tdf-xilinx1-oct12-featim

Vivado, inside the new Xilinx design suite

The FPGA vendor's new flagship is now on public release. It adds an array of features, including support for system-level to HDL synthesis.

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors