hierarchy

December 8, 2014
Block and SOC CDC verification - feat img

Overcoming complex CDC violations with a concurrent block and SoC-level verification flow

CDC violations are now so complex that it takes a combined block and full SoC level verification strategy to catch and fix all the bugs
Article  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations:
April 16, 2014
Real Intent hierarchical CDC

Hierarchy provides a smarter approach to SoC CDC verification

Performing clock-domain crossing (CDC) checks on a flat database is difficult on complex SoCs. Hierarchy improves speed but calls for a smarter approach.
Article  |  Topics: EDA - Verification  |  Tags: ,   |  Organizations:
September 3, 2013
SNPS TDF UPF hierarchy feat img

Choosing a block representation in a UPF-based hierarchical multi-voltage IC design

This article looks at the way in which various representations of a block of a design have different implications in a UPF based power-aware hierarchical design flow.
Article  |  Topics: EDA - IC Implementation  |  Tags: , , ,   |  Organizations:
December 6, 2012

20nm timing analysis – a practical and scalable approach

Using hierarchy and improved constraints management to accelerate static timing analysis at 20nm and below.
Article  |  Topics: EDA Topics, EDA - IC Implementation  |  Tags: , , , ,   |  Organizations:

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