hardware-assisted verification

September 12, 2015
Dr Lauro Rizzatti, verification consultant

Skeet shooting and design debug

In-circuit emulation is attractive but brings with it debug-visibility issues. There are ways to restructure the environment to make bug hunting much more deterministic.
March 17, 2014
Chris Tice is corporate vice president and general manager of hardware system verification at Cadence Design Systems

The rise of hardware-assisted verification

Verification of hardware and software has become a key bottleneck for chip design. Hardware-assisted verification is removing that bottleneck.
Expert Insight  |  Topics: EDA - Verification  |  Tags: ,   |  Organizations:
December 16, 2013
Mick Posner is Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions.

Consistency key to gaining the advantages of IP integration

Consistency is vital to IP integration strategies that rely on developing an SoC using a hierarchy of FPGA-based prototypes.
July 5, 2012
tdf-jul12-flexras-feat

Improving ASIC prototyping on multiple FPGAs through better partitioning

Using a new design-partitioning tool and stacked-silicon interconnect FPGA to develop an ASIC prototyping platform that can be reprogrammed several times a day.
Article  |  Topics: EDA - DFM  |  Tags: , , ,   |  Organizations: ,
April 25, 2012
Mentor's Veloce emulator

Emulation delivers energy efficiencies and economies of scale

Can emulation save energy and space, as well as time, during the verification process? Some argue so.
April 24, 2012
FPGA-based Prototyping Manual

What can FPGA-based prototyping do for you?

This extract from the Synopsys and Xilinx-authored "FPGA-Based Prototyping Methodology Manual" outlines a number of valuable strategies supported by brief project case studies.
April 5, 2012

FPGA prototyping

Building a prototype SoC in one or a set of FPGAs can aid field trials, software development and hardware/software integration. But it's not easy, so the decision to go ahead needs careful consideration.

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