Analysts say there is a $1B market on the horizon. We talk with Mentor's Jean-Marie Brunet about where such a number could come from.
Bus contention and floating busses are well defined issues and therefore excellent candidates for being addressed with early-stage formal verification.
This article shows practical ways to use verification IP for greater productivity with specific code examples from Mentor Graphics' Questa platform.
Research study suggests the maturity of your verification flow determines the likelihood of first-pass success far more than the complexity inherent in design size.
Combining assertion-based verification techniques with emulation makes for easier debug, better coverage and greater functional efficiency.
Lint is no longer just about checking RTL code. It already incorporates functional verification within a three-stage analysis. Time to look again at a 'familiar' technology.
Overcome the time and visibility limitations of simulation and of gate-level and RTL-based strategies to achieve full-chip analysis.
The verification challenge is best addressed by a combination of highly targeted tools, according to Pranav Ashar, CTO of Real Intent.
Functional logic errors remain a significant cause of project delays and re-spins. One of the main reasons is that two important aspects of verification environment quality—the ability to propagate the effect of a bug to an observable point and the ability to observe the faulty effect and thus detect the bug—cannot be analyzed or measured. [...]
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