FSM

January 18, 2016
How to debug and verify finite state machines early in the design flow

Finite state machines: How to debug and verify them early in the flow

Finite State Machines are such a familiar part of design, we can forget how often they generate errors. Learn how to address them quickly and most efficiently
Article  |  Topics: EDA - Verification  |  Tags: , , , , ,   |  Organizations:
January 11, 2016

FPGA design for functional safety

Using triple modular redundancy, error detection and correction, and 'safe' FSMs to ensure greater functional safety in FPGA-based designs
February 26, 2014
Lisa Piper is senior manager of technical marketing at Real Intent.

Complexity drives smart reporting

Increasingly complex state machines are driving the need for smarter ways of reporting errors such as deadlocks and unreachable code in the source RTL.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , , , ,   |  Organizations:

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