formal verification

September 24, 2015
OneSpin HLS and formal verification

Linking high-level synthesis with formal verification

High-level synthesis provides a way to explore hardware architectures to come up with the most efficient implementation for a given situation. But it has taken time for verification techniques to catch up with the idea and ensure design and architecture match.
June 30, 2015
Mark Handover is an applications engineer with Mentor Graphics

Back to basics – doing formal the right way

Considering design style, assertions, engines and coverage can help ease the development of an effective formal verification test plan
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:
May 11, 2015

Verifying clock domain crossings when using fast-to-slow clocks

A look at three techniques to verify the validity of signals moving between clock domains
January 13, 2015
Sarath Kirihennedige, Real Intent

Taking control of constraints verification

Constraints are a vital part of IC design, yet the management and verification of constraints’ quality, completeness, consistency and fidelity to the designer’s intent is an evolving art.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations:
December 1, 2014

Using formal techniques to help tackle SoC verification challenges

Formal techniques can be applied to various parts of the verification challenge, including low-power and clock domain-crossing issues
July 21, 2014
ADAS

When failure is not an option in automotive verification

The ISO 26262 safety standard lays out a number of best practices for the automotive industry and for suppliers. Formal verification provides a way of streamlining the verification of SoCs that need to conform to the standard.
Article  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations:
July 20, 2014
Rebecca Lipon is the senior product marketing manager for the functional verification product line at Synopsys. Prior to joining the marketing team, Rebecca was an applications engineer at Synopsys working on UVM/VMM adoption, VCS, VIP, static and formal verification deployments.

Rethinking SoC verification

The argument for an integrated approach to SoC verification
July 3, 2014
Pranav Ashar

It’s time to embrace objective-driven verification

How Wall Street's vastly resourced IT teams already point the way to cheaper, faster and more efficient verification by putting goals not tools first.
May 28, 2014

Formal verification

As designs get larger and stress the ability of simulation to exercise an SoC, formal techniques have become essential parts of design and verification.
May 19, 2014

Verification coverage

Verification coverage attempts to at least provide a partial answer to the question: "How do you know you are finished verifying?" It involves the combination of a number of techniques.

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