formal verification

August 31, 2017
Ashish Darbari is director of product management at OneSpin Solutions.

Doc Formal: The evolution of formal verification – Part Two

Doc Formal concludes his introduction to formal verification with a practitioner's view of the technology.
July 21, 2017
Ashish Darbari is director of product management at OneSpin Solutions.

Doc Formal: The evolution of formal verification – Part One

Doc Formal begins a two-part series by describing the solid and well-established foundations of formal verification.
June 18, 2017

Portable stimulus

Accellera's Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.
May 22, 2017
Ashish Darbari is director of product management at OneSpin Solutions.

Introducing Doc Formal: the journey so far

Our new columnist introduces himself and traces the progress of formal verification over the last two decades. Join the discussion.
February 23, 2017
Cache verification involves checking multiple scenarios

Cache-coherency checks call on portable stimulus

Portable stimulus and formal verification provide the means to handle the challenge of verifying cache-coherent SoC interconnects.
January 18, 2017
Anders Nordstrom, senior corporate applications engineer, Verification Group, Synopsys

Are you formally connected?

To check the connectivity of an SoC, first you have to define what a connection is...
Expert Insight  |  Topics: IP - Assembly & Integration, EDA - Verification  |  Tags: ,   |  Organizations:
August 28, 2016
Chips on a wafer

Addressing the verification challenges of complex SoCs

Three senior verification specialists talk about how they are navigating the challenge of verifying multibillion-transistor SoCs with limited compute resource, increasing coverage demands and shrinking timescales.
July 5, 2016
Anders Nordstrom, senior corporate applications engineer, Verification Group, Synopsys

Are you formally secure?

A look at how formal verification strategies can be used to check the security feature of complex SoCs for potential data leakage and data integrity issues
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:
May 30, 2016
Anders Nordstrom, senior corporate applications engineer, Verification Group, Synopsys

Comparing your design to itself – a crucial part of verification

Sequential equivalence checking can help trap errors introduced by clock gate insertion, uninitialised registers, and X propagation issues.
January 26, 2016
Bus contention and floating bus issues featured image

Bus contention and floating busses: Catch them before simulation

Bus contention and floating busses are well defined issues and therefore excellent candidates for being addressed with early-stage formal verification.
Article  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations:

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