FD-SOI

January 4, 2016
Dr Walden Rhines is Chairman and CEO of Mentor - A Siemens Business

2015 – The year in review

Dr Walden Rhines, chairman and CEO of Mentor Graphics, opens a two-part analysis by looking back at the dominant design and business trends in 2015.
Expert Insight  |  Topics: EDA Topics  |  Tags: , , , , , ,   |  Organizations:
July 13, 2014
ST/CEA-Leti 'Frisbee' wide-voltage DSP

DVFS and body bias

Dynamic voltage and frequency scaling is effective for low-power VLSI design. Body or back bias can provide additional control over leakage and performance.
Guide  |  Topics: EDA - IC Implementation  |  Tags: , , , ,
July 9, 2014
Intel's trigate is among the structures to be modeled by the revised BSIM4

One BSIM to rule them all

A change in the way the core compact models are developed has accelerated their development and, for the first time, allowed the models to be used not just for circuit simulation but to help guide process evolution as chipmakers play not only with materials but the shape of finFETs.
Article  |  Topics: EDA - DFM, IC Implementation  |  Tags: , , , , , ,   |  Organizations: ,
June 22, 2014
Preview image for monolithic 3D integration

Monolithic 3DIC for SoC

Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
May 29, 2014
Near-threshold computing for minimum energy - thumbnail

Near-threshold and subthreshold logic

By taking the circuit supply voltage close to that of the threshold voltage or even below, it is possible to optimize low-power VLSI design. But there are pitfalls.
May 2, 2013
Intel finfFET SEM

Physical verification of finFET and FD-SOI devices

A look at some of the design and physical verification challenges of working with finFET and FD-SOI devices, including their impact on layout, DRC and LVS.
Article  |  Topics: EDA - Verification  |  Tags: , , ,
December 4, 2012
Dr David M Fried is Chief Technology Officer - Semiconductor at Coventor, responsible for the company’s strategic direction and implementation of its SEMulator3D Virtual Fabrication Platform.

FinFET tipsheet for IEDM

finFETs are vital to the next generation of CMOS processes from Intel, TSMC and others. How will process issues including bulk vs SOI substrates, density limitations, thickness control, and planar device integration affect their practical implementation?
Expert Insight  |  Topics: EDA - DFM  |  Tags: , , , , , , , , ,   |  Organizations:
March 28, 2012

FD-SOI

Fully depleted silicon on insulator (FD-SOI) transistor architectures may offer speed and power advantages, at the cost of a shift to non-standard substrates.
August 23, 2011

Parting of the ways

Intel says ‘trigate’—finFET to others—but depleted silicon-on-insulator also has its post 22nm supporters. Chris Edwards reports on the debate at 2011’s Semicon West.
Article  |  Topics: EDA - IC Implementation  |  Tags: , , , , ,   |  Organizations: ,

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