equivalence checking

May 6, 2015
Formality featimg

Fixing late ECOs in ARM core subsystems at STMicroelectronics

Using equivalence checking to validate ECOs in ARM core subsystem development at STMicroelectronics
May 28, 2014

Formal verification

As designs get larger and stress the ability of simulation to exercise an SoC, formal techniques have become essential parts of design and verification.
July 25, 2013
Dam Benua, Synopsys

Formal techniques tackle the SoC verification challenge

Formal verification techniques are becoming more widely used as the size and complexity of SoCs and increases.

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors