Three senior verification specialists talk about how they are navigating the challenge of verifying multibillion-transistor SoCs with limited compute resource, increasing coverage demands and shrinking timescales.
Emulators have come a long way since their first introduction nearly three decades ago.
What can you add to a challenging project without pushing out deadlines and muddling communication?
Dr Walden Rhines, chairman and CEO of Mentor Graphics, opens a two-part analysis by looking back at the dominant design and business trends in 2015.
More protocols, multibillion-gate designs, minimized power, burgeoning software and, for networking, hundreds of switch and router ports emphasize the need for scalable, virtualized emulation.
Enabling greater reliability, scalability and flexibility of GPU emulation at AMD using a hybrid virtual-machine based approach
How AMD coupled a virtual PC and transaction-based emulation to accelerate the verification of its latest GPU
In-circuit emulation is attractive but brings with it debug-visibility issues. There are ways to restructure the environment to make bug hunting much more deterministic.
Emulation performance is a key metric in verification. But it is far from being the only consideration. How long it takes to get a design onto a verification platform and aspects such as debug are as important. These factors will control how verification platforms are deployed during a project's life cycle.
Emulation is now served by all three leading vendors and is a hot topic for discussion among engineers. The major verification conferences need to follow suit.
Combining assertion-based verification techniques with emulation makes for easier debug, better coverage and greater functional efficiency.
View All Sponsors