Doc Formal sets out the 10 cost points in verification that formal will help you control and reduce.
An introduction to how virtual emulation has fueled the application of co-modeling for complex design verification.
Lauro Rizzatti gets a reality check on AI for both design tools and designs themselves from the formal verification specialist.
In an exclusive interview, Lauro Rizzatti discusses the increasing verification challenges for drone SoCs with Bo Shen, founder of fabless specialist Artosyn.
High-performance vision-processing algorithms need optimized CNN engines to deliver the right performance within the power budget of embedded applications.
Richard Pugh shows how the fast-growing market for drone silicon highlights emulation's power where high data volumes are critical.
How emulation was used to debug out-of-spec power on a multicore ARM design using the AXI bus.
Accellera's Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.
Techniques previously unavailable during ICE or testbench acceleration can now greatly speed emulation debug in those modes.
Portable stimulus and formal verification provide the means to handle the challenge of verifying cache-coherent SoC interconnects.
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