dummy fill

July 23, 2014

20nm

The 20nm node can offer power, performance and area advantages, but making these gains takes a deep understanding of the interactions between process and design.
July 15, 2014

Parasitic extraction

Parasitic extraction reveals the impact of implementation on the theoretical performance of IC designs.
January 13, 2014
Steffen Schulze is director of marketing for Calibre Mask Data Preparation at Mentor Graphics

Consider your options for future nodes

If EUV is further delayed until 8nm, the industry has to explore other options for patterning, and the effects they will have on the DFM flow.
December 3, 2012

Overcoming dummy fill deck limitations for analog design

CSR used a customized approach to automated dummy fill layout for AMS to address layer density and device matching issues in standard flows aimed at digital SoCs.
Article  |  Topics: EDA - DFM, IC Implementation  |  Tags: , ,   |  Organizations: ,
June 1, 2012
Michael Buehler-Garcia

DAC 2012: 20(nm) questions

There's still debate over certain aspects of the 20nm node, but the main challenges are already being addressed. Expect to see foundries and vendors mark their turf at DAC.
Expert Insight  |  Topics: EDA - DFM  |  Tags: , , , , ,   |  Organizations:
May 22, 2012
Jeff Wilson

Making dummy fill smarter

Guest blogger Jeff Wilson discusses some of the subtleties involved in the effective use of dummy fill in deep sub-micron IC designs.
Expert Insight  |  Topics: EDA - DFM  |  Tags: ,   |  Organizations:

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