DRC

April 23, 2018
data validation featured image

The three critical data validation points in a design flow

Why design data integrity matters from cell design to tapeout. These techniques will help ensure your validation process is as comprehensive as possible.
Article  |  Topics: IP - Design Management, EDA - DFM, Verification  |  Tags: , , , , , , , ,   |  Organizations:
January 15, 2018
Physical Verification Efficiencies - featured image

Three ways to lift productivity during physical verification

How to get the best PV results by reducing computational demands; handling data more efficiently and exploiting parallelization.
Article  |  Topics: EDA - DFM, Verification  |  Tags: , , , ,   |  Organizations:
December 22, 2017
feat-im-in-design-DRC

Improve custom/AMS design and productivity with in-design DRC

In-design DRC is a technique that frees up engineers from many of the challenges of delivering AMS design under ever more complex design rules.
Article  |  Topics: EDA - IC Implementation, - Uncategorized  |  Tags: , , , , , ,   |  Organizations:
April 10, 2017
Ron Press is a technical marketing director at Mentor - A Siemens Business. He specializes in DFT and BIST and was the 2010 General Chair of the International Test Conference.

Drawing on hierarchical DFT to benefit all designs and flows

Hierarchical DFT is vital for large, complex designs. Users still to transition to the technique can nevertheless exploit its pattern reuse strategies as they move toward adoption.
Expert Insight  |  Topics: EDA - DFT  |  Tags: , , ,   |  Organizations: ,
July 20, 2015
TSMC finFET

Lessons learned in the finFET trenches

In sessions at the 2015 Design Automation Conference, engineers who had worked on finFET-oriented projects revealed how the technology has changed their design practices and where others may want to think twice about making the move.
May 26, 2014
Unidirectionally routed M1 using SADP (Source: CMU/IBM)

Triple patterning and self-aligned double patterning (SADP)

In the absence of EUV lithography, the primary option for manufacturing on a 10nm process is to extend double patterning. But the options each have issues.
April 3, 2014
Joe Kwan is the Product Marketing Manager for Calibre LFD and Calibre DFM Services at Mentor Graphics.

Standard cell IP must pass the litho-friendly routing test

Lithography is only just beginning to play a role in cell IP selection but early analysis already matters.
April 1, 2013
tdf-ment-waivers-fig1-featim

Improving SoC productivity through automatic design rule waiver processing for legacy IP

You can waive some physical verification errors related to legacy IP found in foundry DRC checks. Knowing which has involved lengthy manual analysis. TSMC is enhancing the process with automation.
Article  |  Topics: IP - Assembly & Integration, EDA - DFM, Verification  |  Tags: , , ,   |  Organizations: ,
June 2, 2011

DRC+: a pattern-based approach to physical verification

DRC+ is a new methodology that algorithmically characterizes design variation through pattern classification. A traditional design rule is used to identify all design structures that share a common configuration. Then, the 2D geometric situations (pattern variations) around the configuration are extracted and classified. Since all such classes share a common configuration, each situation class represents [...]
May 1, 2010

Manufacturing a profit

DFM is essential to differentiating your products in the market, says Luigi Capodieci

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