Ashish Darbari sets out the fundamental qualities of a successful formal verification project.
Still using custom layout or place and route tools here? Ditch that time-consuming practice for a real database merge flow.
Ashish Darbari concludes his series on the need for new verification strategies by considering Debug and Signoff & Review.
Why is verification still such a challenge in spite of all the technologies and techniques being brought to bear
Learn how you can benchmark your design practices against the most successful players in the PCB market - and why you should.
Part three of our series looks at the choices you face as you decide whether to build or buy a board.
Part two of our series on FPGA-based prototyping looks at two critical factors to address before a project begins: budgeting and high-level implementation.
This multi-part series addresses various aspects of FPGA-based prototyping. Future installments will address budgeting and implementation, but we start by looking at why the technique is generating so much interest.
Altera uses standardized design flows to help integrate Intel foundry rules, cut time to tape-out - and speed the evolution of its design flows.
Debug of logic and testbench debug makes up 35% of chip design, and is growing as power-management and hardware/software issues become part of the task.
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