Design Management

December 5, 2017
Ashish Darbari is CEO of formal verification consultancy Axiomise and a Royal Academy of Engineering visiting professor at the University of Southampton.

Doc Formal: the crisis of confidence facing verification III

Ashish Darbari concludes his series on the need for new verification strategies by considering Debug and Signoff & Review.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , , , , , ,   |  Organizations:
October 31, 2017
Ashish Darbari is CEO of formal verification consultancy Axiomise and a Royal Academy of Engineering visiting professor at the University of Southampton.

Doc Formal: The crisis of confidence facing verification

Why is verification still such a challenge in spite of all the technologies and techniques being brought to bear
February 11, 2016
David Wiens is Business Development Manager for the System Design Division at Mentor Graphics.

Where tools end and best practices begin

Learn how you can benchmark your design practices against the most successful players in the PCB market - and why you should.
October 21, 2015
HAPS cables 150

FPGA-based prototyping 3: Which board do I need?

Part three of our series looks at the choices you face as you decide whether to build or buy a board.
September 28, 2015
HAPS cables 150

FPGA-based prototyping 2: Understand the real cost

Part two of our series on FPGA-based prototyping looks at two critical factors to address before a project begins: budgeting and high-level implementation.
September 7, 2015
HAPS cables 150

FPGA-based prototyping 1: What’s all this buzz about?

This multi-part series addresses various aspects of FPGA-based prototyping. Future installments will address budgeting and implementation, but we start by looking at why the technique is generating so much interest.
July 25, 2014
Steven Cline is a senior design automation Manager at Altera’s Austin Technology Center, focusing on design-flow automation for traditionally placed and routed blocks and custom FPGA IP used on Altera’s advanced FPGA products.

Using standardized design flows to cut time to tape-out – and speed design-flow evolution

Altera uses standardized design flows to help integrate Intel foundry rules, cut time to tape-out - and speed the evolution of its design flows.
Expert Insight  |  Topics: IP - Design Management, EDA - IC Implementation  |  Tags: , , , ,   |  Organizations: , ,
April 4, 2013
Michael Sanie, Synopsys

Debugging the debug challenge

Debug of logic and testbench debug makes up 35% of chip design, and is growing as power-management and hardware/software issues become part of the task.
August 23, 2012
Pranav Ashar

Verification challenges require surgical precision

The verification challenge is best addressed by a combination of highly targeted tools, according to Pranav Ashar, CTO of Real Intent.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations:
August 6, 2012
tdf-aug12-mentor-pcb-feat

Concurrent design: one team, one virtual location

Speeding up electronics design by learning lessons in increasing parallelism from computer science.

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