design for test (DFT)

November 16, 2012
Stephen Pateras

IJTAG: delivering an industry platform for IP test and integration

Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
Expert Insight  |  Topics: IP - Assembly & Integration, EDA - DFT  |  Tags: , ,   |  Organizations: ,
November 5, 2012
20nm test feature image

20nm test demands new design-for-test and diagnostic strategies

20nm test needs new approaches to cope with short delay defects, new memory failure mechanisms and the consequences of test compression strategies
Article  |  Topics: EDA - DFT  |  Tags: , , , ,   |  Organizations: , ,
July 3, 2012
Juergen Schloeffel

Why cell-aware testing is important

Characterizing standard-cell defect mechanisms helps improve IC testing
Expert Insight  |  Topics: EDA - DFT  |  Tags: , , ,   |  Organizations:
August 23, 2011
tdf1109_kilopass1_medium

Ensuring the reliability of non-volatile memory in SoC designs

This article describes various non-volatile memory (NVM) intellectual property (IP) alternatives with specific reference to their integration within system-on-chip designs targeting the 65nm process node and below. The article considers many of the strengths and vulnerabilities of these IP options, and then describes the tests that must be undertaken to ensure their long-term reliability, particularly [...]
Article  |  Topics: EDA - DFT, IP - Selection  |  Tags: , , ,   |  Organizations:
February 25, 2011
innovations

Innovations at ITC 2010

Poster sessions are all too often given Cinderella status at major conferences, but they often contain novel and interesting responses to current technology challenges. This article reviews five poster papers that were released at the 2010 International Test Conference ranging in topic from improved device interfaces for gigahertz test to IP security to the diagnosing [...]
Article  |  Topics: EDA - DFT  |  Tags:
December 1, 2009

Silicon test moves up the food chain

Technological advances are often driven by the need to simplify and control a task. Silicon test is a good example. Its requirements are continuously increasing in complexity and this process drives the development and adoption of automated test strategies. A thorough approach to manufacturing test is essential to the delivery of high-quality devices. A whole-chip […]

Article  |  Topics: EDA - DFT  |  Tags: , ,

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