debug

February 6, 2019

Low-power debugging made easy

UPF provides a useful way to describe the power-management strategies that should be applied to a design, but using it introduces a number of challenges during low-power debugging.
Article  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations:
January 7, 2019
Ashish Darbari is CEO of formal verification consultancy Axiomise.

Doc Formal: Introducing the ADEPT FV flow

Escape formal's narrower definitions with a flow that shows you how to Avoid, Detect, Erase, Prove Absence and Tape Out while avoiding bugs.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , , , , ,   |  Organizations:
October 5, 2018
Gate-level simulation feature

How to improve throughput for gate-level simulation

Innovative methodologies, strategies and tool features help overcome other inefficiencies in complex but necessary simulations.
Article  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations:
July 23, 2018
Ashish Darbari is CEO of formal verification consultancy Axiomise.

Doc Formal: The budget case for formal verification

Doc Formal sets out the 10 cost points in verification that formal will help you control and reduce.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations:
May 8, 2018
Ashish Darbari is CEO of formal verification consultancy Axiomise.

Doc Formal: Harness the power of invariant-based bug hunting

Ashish Darbari describes a formal technique that fuels a rapid, predictable and highly effective methodology.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations: ,
December 22, 2017

Improve custom/AMS design and productivity with in-design DRC

In-design DRC is a technique that frees up engineers from many of the challenges of delivering AMS design under ever more complex design rules.
Article  |  Topics: EDA - IC Implementation, - Uncategorized  |  Tags: , , , , , ,   |  Organizations:
December 5, 2017
Ashish Darbari is CEO of formal verification consultancy Axiomise.

Doc Formal: the crisis of confidence facing verification III

Ashish Darbari concludes his series on the need for new verification strategies by considering Debug and Signoff & Review.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , , , , , ,   |  Organizations:
June 13, 2017
Emulation save-and-restore debug featured image

Hardware emulation gets smarter with save-and-restore for debug

Techniques previously unavailable during ICE or testbench acceleration can now greatly speed emulation debug in those modes.
Article  |  Topics: EDA - Verification  |  Tags: , , , , ,   |  Organizations: ,
October 19, 2015
Nasib Naser is senior staff corporate applications engineer in the verification group for Synopsys.

Ten key tips for effective memory verification

Verification IP can help verify that memory-controller implementations meet standards; test an implementation against specific memories; and drive traffic for SoC verification and power analysis. Here's how to choose it.
Expert Insight  |  Topics: IP - Selection, EDA - Verification  |  Tags: , , , , ,   |  Organizations:
August 21, 2015
Visual: cars speeding along a road

Why emulation performance doesn’t matter (on its own)

Emulation performance is a key metric in verification. But it is far from being the only consideration. How long it takes to get a design onto a verification platform and aspects such as debug are as important. These factors will control how verification platforms are deployed during a project's life cycle.

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