constrained random verification (CRV)

May 29, 2015
Mentor Graphics/Wilson Research Group Functional Verification Study

Smaller designs face greater risk of respins

Research study suggests the maturity of your verification flow determines the likelihood of first-pass success far more than the complexity inherent in design size.
May 21, 2012

Where there’s a will… there’s a way to better VHDL verification

An overview of the Open Source VHDL Verification Methodology and two of the libraries it uses.


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