coverage driven verification

January 20, 2015
Veloce2 emulator

Assertion-based emulation

Combining assertion-based verification techniques with emulation makes for easier debug, better coverage and greater functional efficiency.
December 1, 2014
VC formal tools featimg

Using formal techniques to help tackle SoC verification challenges

Formal techniques can be applied to various parts of the verification challenge, including low-power and clock domain-crossing issues
April 4, 2013
Michael Sanie, Synopsys

Debugging the debug challenge

Debug of logic and testbench debug makes up 35% of chip design, and is growing as power-management and hardware/software issues become part of the task.
January 24, 2012

The principles of functional qualification

Functional logic errors remain a significant cause of project delays and re-spins. One of the main reasons is that two important aspects of verification environment quality—the ability to propagate the effect of a bug to an observable point and the ability to observe the faulty effect and thus detect the bug—cannot be analyzed or measured. [...]
December 1, 2008

Tightening the loop on coverage closure

The article describes how methodologies such as graph-based intelligent testbench automation will help engineers efficiently create verification scenarios and stimuli. This is a powerful way of enhancing advanced verification environments and reducing common verification headaches (e.g., reaching coverage goals). Such strategies can help to free up resources, in terms of time, people and hardware, so […]

Article  |  Topics: EDA - Verification  |  Tags: , , ,


Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors