constraints

July 17, 2018
Sean Safarpour is the Director of Application Engineering at Synopsys.

Formal fundamentals: what’s hiding behind your constraints

Effective formal verification demands striking a careful balance in the use of constraints – too many slows things down, but too few may let bugs slip through.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , ,
December 9, 2016
Featured image - analog design constraints

A new path for analog design constraints verification

Traditional techniques are being challenged by shortening design cycles and the effects of later process nodes.
Article  |  Topics: EDA - IC Implementation, Verification  |  Tags: , , ,   |  Organizations:
December 6, 2012

20nm timing analysis – a practical and scalable approach

Using hierarchy and improved constraints management to accelerate static timing analysis at 20nm and below.
Article  |  Topics: EDA Topics, EDA - IC Implementation  |  Tags: , , , ,   |  Organizations:
November 1, 2008

Reducing PCB design cycle by 60%

The PCB design team on Alcatel Shanghai Bell’s recently introduced A7510 Media Gateway product was given only seven weeks to complete its task against an original estimate of 13 weeks. The article describes how the team added new members and adopted a concurrent design strategy to not merely meet but beat the tightened deadline. Specific […]

Article  |  Topics: no topics assigned  |  Tags: , ,
November 1, 2008

Learning the value of preparation and simulation by OSMOSIS

OSMOSIS is a super-fast optical switch developed through the Advanced Simulation and Computing program. The article describes the strategies adopted by the IBM team charged with designing the Central Scheduler board for the project. The design was of a far greater complexity than the team had previously encountered, and as a result, developed new pre-preparation […]

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