clock domain crossing (CDC)

May 31, 2015

Technology trends demand netlist-level CDC verification

Complex processes and aggressive synthesis interventions are increasing the risks of metastability, creating a need for netlist-level CDC verification
May 11, 2015

Verifying clock domain crossings when using fast-to-slow clocks

A look at three techniques to verify the validity of signals moving between clock domains
December 8, 2014

Overcoming complex CDC violations with a concurrent block and SoC-level verification flow

CDC violations are now so complex that it takes a combined block and full SoC level verification strategy to catch and fix all the bugs
Article  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations:
December 1, 2014

Using formal techniques to help tackle SoC verification challenges

Formal techniques can be applied to various parts of the verification challenge, including low-power and clock domain-crossing issues
July 20, 2014
Rebecca Lipon is the senior product marketing manager for the functional verification product line at Synopsys. Prior to joining the marketing team, Rebecca was an applications engineer at Synopsys working on UVM/VMM adoption, VCS, VIP, static and formal verification deployments.

Rethinking SoC verification

The argument for an integrated approach to SoC verification
July 3, 2014
Pranav Ashar

It’s time to embrace objective-driven verification

How Wall Street's vastly resourced IT teams already point the way to cheaper, faster and more efficient verification by putting goals not tools first.
May 28, 2014

Formal verification

As designs get larger and stress the ability of simulation to exercise an SoC, formal techniques have become essential parts of design and verification.
May 19, 2014

On-chip clock strategies and GALS

The increased use of IP and a rise in process variability is driving a move to look at alternatives to traditional low-skew clock distribution strategies.
April 16, 2014
Real Intent hierarchical CDC

Hierarchy provides a smarter approach to SoC CDC verification

Performing clock-domain crossing (CDC) checks on a flat database is difficult on complex SoCs. Hierarchy improves speed but calls for a smarter approach.
Article  |  Topics: EDA - Verification  |  Tags: ,   |  Organizations:
January 27, 2014
Atrenta CDC

Spot the difference between false and real clock violations

Find how to spot some of the most common false clock-domain crossing (CDC) violations and how to efficiently find actual CDC problems that could kill a design if not corrected.
Article  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations:

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors