clock distribution

May 30, 2015

Clock tree synthesis

Clock-tree generation is coming under increased scrutiny because of its role in dynamic power consumption and problems caused by on-chip PVT variation.
April 27, 2015
Enabling FPGA prototyping of large ASIC and SoC designs - featimg

Enabling FPGA prototyping of large ASIC and SoC designs

How tool parallelism, automatic partitioning, deep debug memories and time domain multiplexing eases FPGA prototyping of large ASIC and SoC designs

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