cache coherency

February 23, 2017
Cache verification involves checking multiple scenarios

Cache-coherency checks call on portable stimulus

Portable stimulus and formal verification provide the means to handle the challenge of verifying cache-coherent SoC interconnects.
October 27, 2014

Enabling symmetric multiprocessing for embedded Linux on ARC processor cores

This article looks at some of the key architectural and implementation decisions Synopsys has made in developing a version of its HS series of licensable processor cores to serve the embedded Linux market
Article  |  Topics: Embedded - Architecture & Design, IP - Selection  |  Tags: , , , ,   |  Organizations:
January 15, 2014
Featured image for Debugging with VPs - III

Debugging with virtual prototypes – Part Three

This part illustrates the technique using examples addressing memory corruption, multicore systems and cache coherency with particular reference to watchpoints.
February 5, 2013

Using VIP for cache coherency hardware implementations

Cache coherency implemented in hardware increases the verification effort. VIP-based strategies are described with particular reference to ARM protocols.
Article  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations: ,

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