BIST

August 18, 2012

When good DFT goes bad: debugging broken scan chains

Scan chains help you test complex chip designs. But how do you test the scan chains themselves when they go wrong?
Article  |  Topics: EDA - DFT  |  Tags: , , , ,   |  Organizations:
January 24, 2012

Design for test: a chip-level problem

The inherent complexity of today’s system-on-chips, with their multiple clock and voltage domains, requires test considerations to be moved further up design flows. The article describes strategies for and benefits from apply test before RTL goes through synthesis, augmenting what is already achieved through memory built-in self test and automatic test pattern generation.
Article  |  Topics: EDA - DFT  |  Tags: , , , ,

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