A static-analysis tool that checks for errors in HDL code, lint is becoming an increasingly important addition to simulation for RTL and SoC signoff.
As designs get larger and stress the ability of simulation to exercise an SoC, formal techniques have become essential parts of design and verification.
Verification coverage attempts to at least provide a partial answer to the question: "How do you know you are finished verifying?" It involves the combination of a number of techniques.
More than half of design companies claim to use ABV but many have yet to deploy full methodologies.
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