Doc Formal concludes his introduction to formal verification with a practitioner's view of the technology.
Using formal property verification to prove that SoCs can’t do the wrong thing, as well as that they will do the right thing.
Considering design style, assertions, engines and coverage can help ease the development of an effective formal verification test plan
Research study suggests the maturity of your verification flow determines the likelihood of first-pass success far more than the complexity inherent in design size.
Combining assertion-based verification techniques with emulation makes for easier debug, better coverage and greater functional efficiency.
A static-analysis tool that checks for errors in HDL code, lint is becoming an increasingly important addition to simulation for RTL and SoC signoff.
As designs get larger and stress the ability of simulation to exercise an SoC, formal techniques have become essential parts of design and verification.
Verification coverage attempts to at least provide a partial answer to the question: "How do you know you are finished verifying?" It involves the combination of a number of techniques.
More than half of design companies claim to use ABV but many have yet to deploy full methodologies.
Assertions and assertion-based verification (ABV) are hot topics, but many engineering teams remain unfamiliar with the benefits they bring to the design and verification process. This article discusses the rationale behind them, the value they bring across the design and verification process, and offers a step-by-step approach to implementing them.
View All Sponsors