architecture

December 16, 2013

How high-level synthesis helps optimize low power designs – Part Two

Continuing our series on high-level synthesis (HLS) for low power design. Part Two details how HLS helps you make and evaluate architectural decisions.
January 18, 2013

Get more out of system architectures

This case study shows how the evaluation of various design options requires a thorough approach to system-level modeling.
Article  |  Topics: EDA - ESL  |  Tags: ,   |  Organizations:
May 15, 2012

Decoupled constraint modelling – a design methodology for hard real-time systems on chip

Using UML to define a software-defined modem SoC in terms of decoupled constraints - the order of activities, the timing they have to meet, and the available resources
Article  |  Topics: EDA - DFM  |  Tags: , , , ,
September 10, 2010

Parallel simulation of SystemC TLM 2.0 compliant MPSoCs

Simulation speed is a key issue for the virtual prototyping (VP) of multiprocessor system-on-chips (MPSoCs). The SystemC transaction level modeling (TLM) 2.0 scheme accelerates simulation by using interface method calls (IMC) to implement communication between hardware components. Acceleration can also be achieved using parallel simulation. Multicore workstations are moving into the computing mainstream, and symmetric [...]
Article  |  Topics: IP - Assembly & Integration, EDA - ESL  |  Tags: , ,
June 1, 2010

Winning the power and temperature battle with ESL exploration

The analysis of important power and temperature metrics for chip design is becoming increasingly inefficient when attempted at the register-transfer level. The article proposes the fundamentals of a system-level modeling strategy that will shrink design times, provide more opportunities for architectural exploration, and deliver significant power savings.
Article  |  Topics: EDA - ESL  |  Tags: ,
December 1, 2009

Overcoming the limitations of data introspection for SystemC

The verification, test and debug of SystemC models can be undertaken at an early stage in the design process. To support these techniques, the SystemC Verification Library uses a concept called data introspection. It lets a library routine extract information from SystemC compound types, or a user-specified composite that is derived from a SystemC type. […]

Article  |  Topics: EDA - ESL  |  Tags: ,
June 1, 2009

Bridging from ESL models to implementation via high-level hardware synthesis

The article describes a methodology that bridges the gap between SystemC transaction-level models (TLMs) that are used for architectural exploration and SystemC cycle-accurate models of hardware that typically follow much later in a design flow, after many sensitive decisions have been made. The behavior of the cycle-accurate models can be verified in the complete system […]

Article  |  Topics: EDA - ESL  |  Tags: , ,
June 1, 2009

Using TLM virtual system prototype for hardware and software validation

The article describes how a methodology based around scalable transaction level modeling (TLM) techniques can be used to enable software design to begin far earlier in a design fl ow and thus allow companies to bring designs to market faster, particularly in time-sensitive sectors. It is based on the creation of high-level hardware models that […]

December 1, 2008

Streamlining software development for a hardware ecosystem

Software accounts for more than half the development cost for a complex system-on-chip (SoC) platform at the 45nm process node or below. The availability of fundamental software such as compilers, debuggers, operating systems and industry-specific middleware determines the success or failure of a chip design. In simple terms, if there is little or no software […]

Article  |  Topics: EDA - ESL  |  Tags: , ,

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