analog

September 7, 2022
symmetry verification featim

Interactive checks mean faster, more accurate symmetry verification

Symmetry verification for analog and custom IC needs to evolve beyond current time-consuming and hard-to-use techniques.
Article  |  Topics: EDA Topics, EDA - Verification  |  Tags: , , , , ,   |  Organizations:
March 3, 2022

Why comprehensive memory layout verification needs automated reliability checks

Because of the high analog content in memory designs, designers must understand how various effects impact reliability and performance.
November 4, 2021
UPMEM-PIM-DRAM-featured-image

How UPMEM ensured effective power delivery for its processor-in-memory design

PIM memory boosts efficiency by operating on data without moving it to the CPU but realizing this type of novel technology posed power integration and planning challenges.
March 17, 2020
FeatIm P&R MaxLinear Mentor

How MaxLinear got faster signoff DRC while optimizing reliability and manufacturability

The RF and AMS specialist turned to design software that allowed it to run design checks during place and route.
February 27, 2019

Practical mixed-signal defect and fault injection automation and simulation

This defect and fault injection primer looks at how to standardize definitions, decide injection volume, measure activity, manage simulation, optimize test time and more.
December 22, 2017

Improve custom/AMS design and productivity with in-design DRC

In-design DRC is a technique that frees up engineers from many of the challenges of delivering AMS design under ever more complex design rules.
Article  |  Topics: EDA - IC Implementation  |  Tags: , , , , , ,   |  Organizations:
March 15, 2017
DVCon China takes place at the Parkyard Hotel, Shanghai on April 19th.

DVCon China launches this April in Shanghai

DVCon China general chair Andy Liu discusses Accellera’s new addition to its design and verification conference series (简体中文).
Expert Insight  |  Topics: EDA - ESL, IC Implementation, Verification  |  Tags: , , , , , , ,   |  Organizations: , , ,
March 15, 2017
DVCon China takes place at the Parkyard Hotel, Shanghai on April 19th.

DVCon中国将于4月在上海亮相

DVCon中国大会主席刘红亮讨论了Accellera新增的DVCon中国ASIC设计和验证会议的看点。
Article  |  Topics: EDA - Verification  |  Tags: , , , , , , ,   |  Organizations: , , ,
December 9, 2016
Featured image - analog design constraints

A new path for analog design constraints verification

Traditional techniques are being challenged by shortening design cycles and the effects of later process nodes.
Article  |  Topics: EDA - IC Implementation, Verification  |  Tags: , , ,   |  Organizations:
October 28, 2015
Bruce McGaughy, CTO, ProPlus Design Solutions

FastSPICE simulators hit their expiration date

Although FastSPICE simulators are in almost every design flow, requirements are moving beyond the capabilities they can provide. Parallel processing provides a solution.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations:

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