Doc Formal concludes his introduction to formal verification with a practitioner's view of the technology.
Combining assertion-based verification techniques with emulation makes for easier debug, better coverage and greater functional efficiency.
Better upfront analysis can help avoid propagating errors from RTL into the netlist, and reveal a number of ways to improve the quality of your final design.
Assertions are already used in pre-silicon verification and can help halve debug time. So why not synthesize assertions into real logic gates in the final silicon, to catch those unexpected bugs that make validation so much harder? Here’s how.
The article continues the discussion of the verification requirements within the RTCA DO-254 design assurance guidelines. Part Two focuses on assertion-based verification. It proposes a method for using ABV to meet 'elemental analysis' requirements and underpin a systematic approach to robustness testing.
This two-part article discusses the verification requirements of the RTCA DO-254 design assurance guidelines, including advanced methods for use on class DAL A/B designs. The first part provides a general overview. It also explains the original intent behind the concept of 'elemental analysis', how it is typically satisfied today with code coverage, and the limitations [...]
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