65nm

January 28, 2014
Mark Bollar is a product marketing director at Synopsys overseeing physical implementation.

Are advanced designs only possible at emerging process nodes?

Advanced design isn’t restricted to emerging process nodes any more. Designers are using the latest tools to produce advanced designs on established nodes.
October 2, 2013

Catching layout-dependent effects on-the-fly

New layout-dependent effects (LDEs) arise at each process node. This methodology updates LDE parameters and uses on-the-fly simulation for early detection.
Article  |  Topics: EDA - DFM, IC Implementation  |  Tags: , , , ,   |  Organizations:
August 23, 2011

Ensuring the reliability of non-volatile memory in SoC designs

This article describes various non-volatile memory (NVM) intellectual property (IP) alternatives with specific reference to their integration within system-on-chip designs targeting the 65nm process node and below. The article considers many of the strengths and vulnerabilities of these IP options, and then describes the tests that must be undertaken to ensure their long-term reliability, particularly [...]
Article  |  Topics: EDA - DFT, IP - Selection  |  Tags: , , ,   |  Organizations:
May 1, 2010

Using DFM for competitive advantage

The article offers a case study of the DFM planning and methodology applied during a shrink of Cambridge Silicon Radio's UF6000 system-on-chip from the 130nm to 65nm.
Article  |  Topics: EDA - DFM  |  Tags: , , , , , ,   |  Organizations: ,

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