November 24, 2017
John Ferguson is the Director of Marketing for Calibre DRC Applications at Mentor, a Siemens Business, in Wilsonville, Oregon, with extensive experience in physical design verification. He holds a BS degree in Physics from McGill University, an MS in Applied Physics from the University of Massachusetts, and a PhD in Electrical Engineering from the Oregon Graduate Institute of Science and Technology.

Assessing the true cost of node transitions

John Ferguson reviews the key capital metrics you need to review when deciding whether to move to a new process.
July 23, 2014


The 20nm node can offer power, performance and area advantages, but making these gains takes a deep understanding of the interactions between process and design.
January 13, 2014
Interconnect resistance has increased since the 40nm node

Interconnect resistance

A number of effects have led to a dramatic increase in interconnect resistance in the sub-32nm process nodes that demands the use of smarter routing.
October 16, 2013
Piyush Sancheti, vice president of product marketing at Atrenta.

The requirements for complete RTL signoff

Problems become expensive to fix after the place-and-route stage so it's time to think seriously about the role of RTL signoff within the design flow.
Expert Insight  |  Topics: EDA - IC Implementation, Verification  |  Tags: ,   |  Organizations:
September 24, 2013
TDF- Synopsys - BULL - feat

Accelerating process migration in advanced ASIC design at Bull

How the HPC company used Synopsys' Lynx Design System to standardise its flow and simplify migration to the next node.
Article  |  Topics: IP - Design Management, EDA - IC Implementation  |  Tags: , , ,   |  Organizations: ,
April 1, 2013

Improving SoC productivity through automatic design rule waiver processing for legacy IP

You can waive some physical verification errors related to legacy IP found in foundry DRC checks. Knowing which has involved lengthy manual analysis. TSMC is enhancing the process with automation.
Article  |  Topics: IP - Assembly & Integration, EDA - DFM, Verification  |  Tags: , , ,   |  Organizations: ,
June 1, 2011

The challenge of analog, mixed-signal and custom physical implementation at 28nm

The 28nm process node has once more raised the design bar in terms of the DFM checks needed to realize a design. This is particularly true for analog and mixed-signal engineering, where rules that could once be maintained manually now need to be addressed in a more integrated, automated, and timely way. The article explores [...]
Article  |  Topics: EDA - IC Implementation  |  Tags: , ,


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