Guides - Techniques

X propagation within RTL simulations can hide fatal bugs. Uncovering and eliminating the effect improves design quality and avoids respins.

Accounting for on-chip variation (OCV) has become a critical factor in assuring timing closure for nanometer-scale ICs and avoiding over-pessimistic margins.

Real-valued modelling provides a way of speeding up the simulation of SoCs with significant analog content through the use of discrete-event solvers.

The technique enables early software development and hardware/software co-design strategies before a project is more rigidly defined in RTL.

For a growing number of applications, leakage is a major component of the lifetime energy consumption of an MCU, making it essential to shut the processor core down when it is not needed. Sleep modes help control that.

A side-channel attack is a form of reverse engineering that takes advantage of the information leakage from electronic circuitry. And it is a major risk to design security.

The value of the emulation market has almost doubled in the last four years as the technique becomes increasingly valuable to hardware/software co-verification.

The scheduler is a key component of any real-time operating system (RTOS). This guide describes the concepts employed by common schedulers and the policies they employ.

More than half of design companies claim to use ABV but many have yet to deploy full methodologies.

Building a prototype SoC in one or a set of FPGAs can aid field trials, software development and hardware/software integration. But it's not easy, so the decision to go ahead needs careful consideration.