How Synplify makes it easier to use IP in FPGA-based designs, and package your own IP for secure reuse, on Altera and Xilinx devices
Designers working on automotive ICs, to be built on established processes, can benefit from the power of design tools developed for advanced processes.
How ST Microelectronics uses Synopsys' VCS AMS, combining VCS functional verification and CustomSim, to verify one of its mixed-signal designs
A look at the challenges of designing chips for the Internet of Things, or IoT, and some of the responses to those challenges
CDC violations are now so complex that it takes a combined block and full SoC level verification strategy to catch and fix all the bugs
Formal techniques can be applied to various parts of the verification challenge, including low-power and clock domain-crossing issues
Need to convince your FD of emulation’s growing ROI and the need to invest? Click here and ‘Forward’
A look under the hood of IC Compiler II, Synopsys' next-generation netlist-to-GDSII implementation system.
This article looks at some of the key architectural and implementation decisions Synopsys has made in developing a version of its HS series of licensable processor cores to serve the embedded Linux market
A look at a tool and a flow that makes it easier to put designs on to a HAPS physical prototyping system for verification, debug and software development purposes
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