Synopsys

February 27, 2015
IP based design with Synplify - featimg

Getting the most out of IP based FPGA design with Synplify

How Synplify makes it easier to use IP in FPGA-based designs, and package your own IP for secure reuse, on Altera and Xilinx devices
Article  |  Topics: IP - Assembly & Integration, Design Management  |  Tags: , , , , ,   |  Organizations:
February 3, 2015
Marco Casale-Rossi is a senior staff product marketing manager in the Design Group at Synopsys.

Automotive ICs drive advanced design at established nodes

Designers working on automotive ICs, to be built on established processes, can benefit from the power of design tools developed for advanced processes.
Expert Insight  |  Topics: EDA - IC Implementation  |  Tags: , ,   |  Organizations:
January 30, 2015
VCS AMS feat img

Mixed-signal verification of advanced SoCs using VCS AMS

How ST Microelectronics uses Synopsys' VCS AMS, combining VCS functional verification and CustomSim, to verify one of its mixed-signal designs
Article  |  Topics: IP Topics, EDA - Verification  |  Tags: , , , , ,   |  Organizations: ,
January 7, 2015
Expert Insight - Holisitic approach to IoT chip design_feat img.jpg

A holistic approach to IoT chip design

A look at the challenges of designing chips for the Internet of Things, or IoT, and some of the responses to those challenges
December 8, 2014
Block and SOC CDC verification - feat img

Overcoming complex CDC violations with a concurrent block and SoC-level verification flow

CDC violations are now so complex that it takes a combined block and full SoC level verification strategy to catch and fix all the bugs
Article  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations:
December 1, 2014
VC formal tools featimg

Using formal techniques to help tackle SoC verification challenges

Formal techniques can be applied to various parts of the verification challenge, including low-power and clock domain-crossing issues
November 6, 2014
Dr Lauro Rizzatti is an independent verification consultant. You can contact him at lauro AT rizzatti DOT com

The budget case for emulation

Need to convince your FD of emulation’s growing ROI and the need to invest? Click here and ‘Forward’
October 31, 2014
Short introduction to IC Compiler II - featimg

A short introduction to IC Compiler II

A look under the hood of IC Compiler II, Synopsys' next-generation netlist-to-GDSII implementation system.
October 27, 2014
Enabling symmetric multiprocessing for embedded Linux on ARC processor cores feature image

Enabling symmetric multiprocessing for embedded Linux on ARC processor cores

This article looks at some of the key architectural and implementation decisions Synopsys has made in developing a version of its HS series of licensable processor cores to serve the embedded Linux market
Article  |  Topics: Embedded - Architecture & Design, IP - Selection  |  Tags: , , , ,   |  Organizations:
October 15, 2014
ProtoCompiler featimg

Accelerating ‘time to prototype’ with ProtoCompiler

A look at a tool and a flow that makes it easier to put designs on to a HAPS physical prototyping system for verification, debug and software development purposes

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors