Synopsys

August 26, 2015
Gervais Fong is a senior product manager for mixed-signal PHY IP at Synopsys.

USB Type-C: easier for users, harder for designers

Implementing the reversible connector of USB Type-C demands a rethink of the PHY architecture to achieve the most cost-effective IP solution
Expert Insight  |  Topics: IP - Selection  |  Tags: , , , ,   |  Organizations:
August 19, 2015
Jai Durgam, Synopsys

Make vs buy in automotive IP

A look at some of the quality and safety requirements that must be met when developing and applying semiconductor IP to the automotive sector.
Expert Insight  |  Topics: IP Topics, IP - Selection, EDA - Verification  |  Tags: , , , , , ,   |  Organizations:
August 7, 2015
Automotive crash test

Improving functional safety of automotive systems using virtual prototyping

The increasing complexity of automative software is challenging the ability of established software testing strategies to demonstrate its functional safety. Here's how virtual prototyping can help.
Article  |  Topics: EDA - Verification  |  Tags: , , , , , ,   |  Organizations:
August 4, 2015
Mick Posner is Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions.

Building better debug facilities for bigger FPGA-based prototypes

The introduction of bigger FPGAs enables more complex prototypes - but makes debugging more of a challenge. Here's one way to address the issue.
Expert Insight  |  Topics: EDA - Verification  |  Tags: ,   |  Organizations: ,
June 22, 2015
Synopsys MIPI verification featimg

Verifying MIPI interfaces in SoCs

Verifying MIPI interfaces including CSI-2, CPHY, DPHY, MPY, Unipro and the UFS host controller on complex SoCs - should you make or buy the necessary VIP?
Article  |  Topics: IP - Selection, EDA - Verification  |  Tags: , , , , , , , ,   |  Organizations: ,
June 17, 2015
Joe Mallett is senior manager, product marketing for FPGA-based synthesis software tools at Synopsys.

Eight tips for choosing your next FPGA tool

Eight issues to consider when choosing an FPGA tool, including risk minimisation, routing issues, ability to iterate, IP freedom and more
Expert Insight  |  Topics: EDA Topics  |  Tags: , ,   |  Organizations:
May 6, 2015
Formality featimg

Fixing late ECOs in ARM core subsystems at STMicroelectronics

Using equivalence checking to validate ECOs in ARM core subsystem development at STMicroelectronics
April 30, 2015
Dr Lauro Rizzatti is an independent verification consultant. You can contact him at lauro AT rizzatti DOT com

Putting emulation on the map

Emulation is now served by all three leading vendors and is a hot topic for discussion among engineers. The major verification conferences need to follow suit.
Expert Insight  |  Topics: EDA - ESL, IC Implementation, Verification  |  Tags: , ,   |  Organizations: , ,
April 20, 2015
Prototyping Imagination GPUs - featimg

Developing and integrating configurable GPU IP using FPGA-based prototyping

How Imagination Technologies used FPGA-based prototyping to develop its GPU IP and integrate it into a real world system
April 3, 2015
Early and accurate power estimation - feat img

A better method for early and accurate power estimation

Early and accurate SoC power estimation is possible, says Broadcom, thanks to a technique that maps simulation results between gate and RTL representations
Article  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations: ,

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