Synopsys

May 6, 2015
Formality featimg

Fixing late ECOs in ARM core subsystems at STMicroelectronics

Using equivalence checking to validate ECOs in ARM core subsystem development at STMicroelectronics
April 30, 2015
Dr Lauro Rizzatti is an independent verification consultant. You can contact him at lauro AT rizzatti DOT com

Putting emulation on the map

Emulation is now served by all three leading vendors and is a hot topic for discussion among engineers. The major verification conferences need to follow suit.
Expert Insight  |  Topics: EDA - ESL, IC Implementation, Verification  |  Tags: , ,   |  Organizations: , ,
April 20, 2015
Prototyping Imagination GPUs - featimg

Developing and integrating configurable GPU IP using FPGA-based prototyping

How Imagination Technologies used FPGA-based prototyping to develop its GPU IP and integrate it into a real world system
April 3, 2015
Early and accurate power estimation - feat img

A better method for early and accurate power estimation

Early and accurate SoC power estimation is possible, says Broadcom, thanks to a technique that maps simulation results between gate and RTL representations
Article  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations: ,
February 27, 2015
IP based design with Synplify - featimg

Getting the most out of IP based FPGA design with Synplify

How Synplify makes it easier to use IP in FPGA-based designs, and package your own IP for secure reuse, on Altera and Xilinx devices
Article  |  Topics: IP - Assembly & Integration, Design Management  |  Tags: , , , , ,   |  Organizations:
February 3, 2015
Marco Casale-Rossi is a senior staff product marketing manager in the Design Group at Synopsys.

Automotive ICs drive advanced design at established nodes

Designers working on automotive ICs, to be built on established processes, can benefit from the power of design tools developed for advanced processes.
Expert Insight  |  Topics: EDA - IC Implementation  |  Tags: , ,   |  Organizations:
January 30, 2015
VCS AMS feat img

Mixed-signal verification of advanced SoCs using VCS AMS

How ST Microelectronics uses Synopsys' VCS AMS, combining VCS functional verification and CustomSim, to verify one of its mixed-signal designs
Article  |  Topics: IP Topics, EDA - Verification  |  Tags: , , , , ,   |  Organizations: ,
January 7, 2015
Expert Insight - Holisitic approach to IoT chip design_feat img.jpg

A holistic approach to IoT chip design

A look at the challenges of designing chips for the Internet of Things, or IoT, and some of the responses to those challenges
December 8, 2014
Block and SOC CDC verification - feat img

Overcoming complex CDC violations with a concurrent block and SoC-level verification flow

CDC violations are now so complex that it takes a combined block and full SoC level verification strategy to catch and fix all the bugs
Article  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations:
December 1, 2014
VC formal tools featimg

Using formal techniques to help tackle SoC verification challenges

Formal techniques can be applied to various parts of the verification challenge, including low-power and clock domain-crossing issues

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