Synopsys

December 2, 2016

Hierarchical signoff of SoC designs at advanced process nodes

Hierarchical signoff strategies for large SoCs at advanced nodes can be effective if sufficient attention is paid to reflecting the impact of cross-hierarchy parasitics.
November 29, 2016
Ken Brock, product marketing manager, Synopsys

Six ways to exploit the advantages of finFETs

FinFET processes and libraries are maturing, enabling designers to explore the best ways to take advantage of the capabilities of the new transistor design
Expert Insight  |  Topics: EDA - IC Implementation, IP - Selection  |  Tags: , , ,   |  Organizations: ,
November 22, 2016
Visual: cars speeding along a road

Implementing DDR DRAM in automotive applications

A look at how DDR DRAM is being adapted for use in automotive systems, and the demands its use puts upon interface IP for SoCs.
Article  |  Topics: IP Topics, IP - Selection  |  Tags: , , , , ,   |  Organizations: ,
November 21, 2016
Brian Davenport is a staff engineer in Synopsys’ Verification Group focusing on automotive functional safety solutions and technologies.

How functional safety verification helps us build safer cars

Considering the issue of functional safety verification in automotive systems design, within the context of ISO26262
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:
October 27, 2016
Ron Lowman, strategic marketing manager for IoT, Synopsys

Exploring the advantages of monolithic Bluetooth low energy radio integration

A look at implementing Bluetooth low energy interfaces into a design and the trade-offs involved in making different levels of integration
Expert Insight  |  Topics: Embedded - Architecture & Design, IP - Selection  |  Tags: , ,   |  Organizations: ,
September 29, 2016
Visual: cars speeding along a road

The challenges of automotive functional safety verification

Engineers developing an SoC for the automotive market have to show that it doesn’t have functional safety issues - even if the SoC enters an unexpected state. Here's how to tackle the safety verification task.
Article  |  Topics: EDA - Verification  |  Tags: , , , , ,   |  Organizations:
August 28, 2016
Chips on a wafer

Addressing the verification challenges of complex SoCs

Three senior verification specialists talk about how they are navigating the challenge of verifying multibillion-transistor SoCs with limited compute resource, increasing coverage demands and shrinking timescales.
July 29, 2016

Hardware roots of trust for IoT security

IoT security is critical. Embedding a root of trust in hardware can provide the firm foundation necessary for a more secure IoT implementation.
July 22, 2016
Dr Lauro Rizzatti, verification consultant

The emulator thrives as verification models mushroom

Emulators have come a long way since their first introduction nearly three decades ago.
July 13, 2016
Hezi Saar is a staff product marketing manager at Synopsys responsible for its DesignWare MIPI controller and PHY IP product line.

I3C specification updates I2C for sensor subsystems

A look at the ways in which the I2C serial interface specification is being updated to form I3C, and its use in sensor subsystems
Expert Insight  |  Topics: IP - Selection  |  Tags: , ,   |  Organizations: ,

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